本篇幫寫論文-CMOS的結構變化講了前幾代CMOS目前正在全球的實驗室中進行研究。本文的研究人員建議對器件的結構進行改變，如向DG FET、thin SOI和地平面FET的轉變，以增加其功能，並緩解部分限制(Wang et al.， 2013)。從本文的回顧中可以斷言，這些設備的結構變化可以使CMOS從一代擴展到三代。
The previous generations of the CMOS are presently being explored within the labs of research across the globe. The structural changes of the device such as the shift towards the DG FET, thin SOI and the FET of ground plane are suggested by the researchers of article to increase the functionality and provide with relief for some of the limitation (Wang et al., 2013). It can be asserted from the review of article that these structural changes of the device can enable extension of the CMOS from one to three more generations. However, it is pointed out by the researchers that its extension brings out varied set of challenges that are required to be considered and mitigated. These difficulties and challenges are controlling the thickness of the silicon channel and the three dimensional form of devices controlling with the use of layer by the form of processes and planar.
The researchers have established that the layout of mask for certain of the identified new structures can be more inclined towards being incompatible with the designs that are existing (Wong et al., 2005). Hence, this will create the need for the expenditure of large redesigning. It is suggested that the technology of silicon that had been using the limited and same set of material from the previous several years will be in a need of newer materials, particularly for the gate in order to implement the latest structures. However, the materials like the Siege can still be utilized for the purpose of performance enhancement upon the stoppage of the scaling.
The article analysed the effects of the dopant fluctuation (Aibin et al., 2015). This analysis suggested that the projections of the industry for the supply voltage reduction are highly optimistic. It is to take into account that uncertainty of expected parameter takes place because of the physics of fundamental nature. This can be understood as the process tolerances and fluctuation of dopant that combines with the large number of devices for each of the chip.
This specific challenge emerges in a partial manner due to the expectation and assumption that the voltage of the power supply will be lowered to the value that is similar to the threshold voltage (Jiang et al., 2015). The solution could be realized though maintaining the value of reasonable nature being VDD-VT or the alleviation of the effects of dopant fluctuation from the structures of the innovative device.